The present invention relates to an automatic gain control circuit which is able to assure a good receiving operation by optimizing a follow-up performance of an automatic gain control loop, a receiver device with the automatic gain control circuit, an automatic gain control method in the receiver device, and a recording medium for recording a program for carrying out the automatic gain control method.
As the automatic gain control circuit in the receiver device in the prior art, the circuit as shown in FIG. 13 has been well known, for example. In FIG. 13, the automatic gain control circuit in the prior art is constructed to comprises a gain variable amplifier 11, a demodulator portion 12, an A/D converter 13, a level detector 14, an averaging portion 15, an adder 16 for calculating a difference-in-converged value, a multiplier 17 for controlling a loop gain, an adder 18 in an integrator circuit portion, a latch circuit 19 in an integrator circuit portion, an arithmetic portion 20, and a D/A converter 21.
In the automatic gain control circuit in the prior art, when a receiving signal Ri is input, such receiving signal input Ri is amplified by the gain variable amplifier 11, then demodulated by the demodulator portion 12, and then converted into a digital value by the A/D converter 13 to be output as a demodulated output Rd. A part of the demodulated output Rd is level-detected by the level detector 14 and then send out to an automatic gain control loop.
The level-detected data are averaged for a predetermined time by the averaging portion 15. Then, a difference between an output of the averaging portion 15 and a constant target level A is calculated by the difference-in-converged value calculating adder 16 so as to converge the output to the input for the A/D converter 13, and then multiplied by a loop gain control value B in the automatic gain control circuit by the loop gain controlling multiplier 17. An output of the multiplier 17 is input into an integrator circuit portion, which consists of the adder 18 and the latch circuit 19, as an amount of change from the preceding data, and then integral data are latched by the latch circuit 19 at a timing of a latch timing control value C4. The integral data from the integrator circuit portion are converted into data equivalent to the control voltage for the gain variable amplifier 11 by the arithmetic portion 20, then converted into an analogue voltage by the D/A converter 21, and then fed back to the gain variable amplifier 11 as the control voltage.
However, in the above automatic gain control circuit in the prior art, a generation or update period of the control signal which is fed back to the gain variable amplifier 11 is fixed. For this reason, when variation in level of the receiving signal Ri is largely caused at the time of a turn-ON operation of a power supply of the automatic gain control circuit, an intermittent receiving operation of the receiver device which includes the automatic gain control circuit, a receiving operation in the fading condition, or the like, a follow-up performance of the automatic gain control loop is degraded in the event that the generation or update period of the control signal of the automatic gain control loop is set and fixed as a relatively large value, conversely the follow-up performance of the automatic gain control loop is made too quick so that there is a possibility to cause harmful influences such as generation of an unstable state, generation of oscillation, etc. in the event that the generation or update period of the control signal of the automatic gain control loop is set and fixed as a relatively small value.